System for digital television broadcasting using modified 2/3 trellis coding

ABSTRACT

Serially concatenated convolutional coding (SCCC) transmitting ancillary data within DTV signals incorporates the ⅔ trellis coding used for all DTV signals as its inner convolutional coding. The outer convolutional coding of the SCCC is subjected to _“anti-Gray”_ coding, either before or after its interleaving, but before its inner convolutional coding. In a receiver for ancillary data as so transmitted, simple logic circuitry recodes portions of the trellis decoded DTV signal containing soft decisions as to the symbol-interleaved convolutionally coded ancillary data to provide a Gray-code mapping of symbols to modulation levels. This recoding is done either before or after symbol de-interleaving, but before decoding the outer convolutional coding to recover ancillary data. Soft decisions concerning extrinsic information to be fed back to the ⅔ trellis decoder to close a turbo decoding loop are derived from soft decisions as to the ancillary data, and this derivation includes recoding for a binary-code mapping of symbols to modulation levels.

This application is filed under 35 U.S.C. 111(a) claiming, pursuant to35 U.S.C. 119(e)(1), benefit of the filing date of provisional U.S.patent application Ser. No. 61/133,294 filed pursuant to 35 U.S.C.111(b) on Jun. 27, 2008.

The invention relates to over-the-air broadcasting of digital television(DTV) signals and more particularly to receivers for such broadcast DTVsignals.

BACKGROUND OF THE INVENTION

The Advanced Television Systems Committee (ATSC) published a DigitalTelevision Standard in 1995 as Document A/53, hereinafter referred tosimply as “A/53” for sake of brevity Digital television. A/53 specifiesthe eight-level-modulation vestigial-sideband amplitude-modulationsignals known as “8VSB” signals that are used for over-the-air DTVbroadcasting in the United States of America. In late May 2009 ATSCcompleted the writing of a “Candidate Standard: ATSC Mobile DTVStandard”, referred to hereinafter simply as “A/153” for sake ofbrevity, which candidate standard is incorporated herein by reference.

A/153 is directed to transmitting ancillary signals in time divisionmultiplex with 8VSB DTV signals, which ancillary signals are designedfor reception by mobile receivers and by hand-held receivers. Theancillary data employ internet protocol (IP) transport streams. Theancillary data are randomized and subjected to transverse Reed-Solomon(TRS) forward-error-correction (FEC) coding before serially concatenatedconvolutional coding (SCCC). The SCCC incorporates the 12-phase ⅔trellis coding of 8VSB as inner convolutional coding followingsingle-phase outer convolutional coding and intermediatesymbol-interleaving procedures. The symbol-interleaved outerconvolutional coding is time-division multiplexed into 8VSB DTV signalso as not to be subject to the convolutional byte interleavingprescribed by Section 4.2.5 of Annex D of A/53 and applied to the mainDTV signal.

The 8-level symbol mapping specified in A/53 and in A/153 maps eachgroup of Z₂, Z₁ and Z₀ bits into a respective eight-level VSB symbol inaccordance with simple binary coding. This results in the Z₂ and Z₂ bitsof original data both changing value between the 011 and 100 levels.This makes a double-bit error likely when noise causes an adjacent-binerror during data slicing in this region of the symbol map. OnlyReed-Solomon coding with 8-bit bytes is concatenated after the ⅔ trelliscoding in ordinary 8VSB transmissions as specified by A/53, so thedouble-bit errors being within single bytes affect overall coding beingfound correct no more than single-bit errors within single bytes.However, when further convolutional coding is introduced before the ⅔trellis coding at the transmitter, the double-bit errors are moredisruptive than single-bit errors when decoding that furtherconvolutional coding in the receiver.

Digital transmission systems using multi-level symbols generated by Graycoding are known. An adjacent-bin error will cause only a single-biterror in an 8-level symbol using Gray code symbol mapping, rather than adouble-bit or triple-bit error. However, symbol mapping using Gray codeover all eight modulation levels is incompatible with the ⅔ trelliscoding of ordinary 8VSB coding. The ⅔ trellis coding must be maintainedso as not to disrupt the operations of receivers already in the fieldthat were designed for receiving ordinary 8VSB signals broadcast perA/53. So, initially, the inventor was unable to discern how to utilizeeffectively the general idea of avoiding an adjacent-bin error duringdata slicing generating double-bit errors in a special type of turbocoding designed for digital television broadcasting.

After further consideration, the inventor was able to figure out how toavoid generating double-bit errors in symbols each composed of a Z-sub-2bit and a Z-sub-1 bit, which errors arise from adjacent-bin errorsduring data slicing. Each 2-bit symbol composed of a Z-sub-2 bit and aZ-sub-1 bit could be anti-Gray coded before ⅔ trellis coding in the DTVtransmitter. Then, subsequent to ⅔ trellis decoding in the DTV receiver,each 2-bit symbol could be Gray coded to counter the effects of theanti-Gray coding. The symbol mapping into modulation levels is convertedto Gray coding insofar as the two more significant bits of the 3-bitsymbols are concerned. This procedure extends the effects of the ⅔trellis decoding from just the Z-sub-1 bits to the Z-sub-2 bits as well,in a unique way quite different from the prior art.

U.S. Pat. No. 5,825,832 issued 20 Oct. 1998 to V. Benedetto and titled“Method and device for the reception of signals affected by inter-symbolinterface” describes decoding procedures for serially concatenatedconvolutional coding (SCCC) that use cascaded Viterbi decoders, but donot employ a turbo decoding loop. A first Viterbi decoder supplies harddecisions as to the transmitted symbols accompanied by a reliabilityparameter. This soft-decision output from the first Viterbi decoder,which is essentially intended to take into account the memory effects ofthe channel by counteracting the effects of inter-symbol interference,is fed after de-interleaving to a second Viterbi decoder which carriesout the actual decision. This decoding operation corresponds to theopen-loop operation of a turbo decoding loop for SCCC. Interestingly,using single-dimension symbol mapping defined according to consecutivebinary numbers will aid the first Viterbi decoder in its task ofcounteracting the effects of inter-symbol interference, since there aremore transition points in the coded bits than there are usingsingle-dimension symbol mapping defined according to Gray coding. Theconversion of the symbol mapping after the first Viterbi decoder, so thesecond Viterbi decoder is presented with single-dimension symbol mappingdefined according to Gray coding will benefit the second Viterbi decodermaking actual decisions. This is because there are fewer transitionpoints in the coded bits to affect decisions than with single-dimensionsymbol mapping defined according to consecutive binary numbers.Accordingly, there is apt to be a reduction in the number of decodingiterations required when turbo decoding procedures are implemented.Possibly, there will be some reduction in the SNR required to achievesatisfactory reception.

No matter what type of symbol mapping is used, the ⅔ trellis codingprovides information for resolving adjacent-bin errors. When thecorruption of the 8VSB symbols by noise is not severe, a DTV receiverwill be able to decode the ⅔ trellis coding and correct adjacent-binerrors in the coded symbols, whether the errors be double-bit orsingle-bit in nature. When a spike of noise energy or a drop-out inreceived signal obliterates a few 8VSB symbols or causes distant-binerrors in the coded symbols, the information for resolving adjacent-binerrors in subsequent symbols is corrupted and is apt to generaterecurring error for some time. The code pattern will probably eventuallybe such that the error would self correct. Similar effects occur for theconvolutional outer coding.

In some DTV receiver designs, in order to shorten the time to recoverfrom a spike of noise energy or a drop-out in received signal, theresults of data-slicing 8VSB symbols are used to start the ⅔ trellisdecoding procedure over. Gray coding the hard-decision portions of theresults of data-slicing 8VSB symbols, as expressed in the soft decisionsfrom the decoder for the inner convolutional coding, benefits thedecoder for the outer convolutional coding. This is because theprobability of error in the least significant bit of the symbolextracted from data slicing is reduced by at least one third.

There has been considerable development work done in DTV receiver designthat incorporates the Viterbi decoder for the ⅔ trellis coding ofordinary 8VSB coding into the adaptive channel equalization filteringused to counteract the effects of inter-symbol interference. Deferringsingle-dimension symbol mapping being defined according to Gray codinguntil after both adaptive channel equalization and the Viterbi decodingprocedure used to implement the adaptive channel equalization preservesthe benefits of that previous development work.

After the inventor's insight into how to avoid an adjacent-bin errorduring data slicing generating double-bit errors in symbols eachcomposed of a Z-sub-2 bit and a Z-sub-1 bit, there remained furtherproblems of designing DTV transmitter and DTV receiver configurations toexploit the insight. U.S. patent application Ser. No. 11/978,462 titled“System for digital television broadcasting using modified ⅔ trelliscoding” and filed by A. L. R. Limberg on 29 Oct. 2007 was published 15May 2008 with publication No. US-2008-0112502-A1. The DTV receiverdesigns described in application Ser. No. 11/978,462 recode softdecisions from the ⅔ trellis decoder to generate interleaved outercoding for subsequent de-interleaving and decoding. This recoding isdescribed as being performed by read-only memory (ROM) addressed bytwo-bit symbols. The inventor subsequently found that this recoding isbetter performed by ROM addressed by each successive complete softdecision supplied by the ⅔ trellis decoder. The DTV receiver designsdescribed in application Ser. No. 11/978,462 recode soft decisions fromthe outer SISO decoder for subsequent derivation of extrinsicinformation fed back to the ⅔ trellis decoder to implement turbodecoding. This recoding is described as also being performed byread-only memory addressed by two-bit symbols. The inventor subsequentlyfound that this recoding also is better performed by ROM addressed byeach successive complete soft decision supplied by the outer SISOdecoder. That is, the ROMs used for recoding need to be addressed by theseveral bits descriptive of the two soft bits in each soft decision theyare to recode.

The ROMs used for recoding become quite large when addressed by theseveral bits descriptive of the two soft bits in each soft decision theyare to recode. E.g., addressing can be sixteen bits wide. However, theinventor subsequently discerned that simple logic circuitry could beused for recoding symbols from a mapping for binary-code modulation to amapping for reflected-binary-code modulation—i.e., for Gray-codemodulation—or vice versa. Recoders using such simple logic circuitry areused in receivers that embody the invention in its preferred forms.

SUMMARY OF THE INVENTION

Serially concatenated convolutional code (SCCC) signals are used totransmit ancillary data within DTV signals using SCCC that incorporatesthe ⅔ trellis coding used for all DTV signals as inner convolutionalcoding for the SCCC. The SCCC'd ancillary data are transmitted so as tobe free of convolutional byte interleaving prescribed by Section 4.2.5of Annex D of A/53. The outer convolutional coding of the SCCC issubjected to anti-Gray coding, either before or after its interleaving,but before its inner convolutional coding. The invention is directedtowards receivers for ancillary data as so transmitted. In such areceiver portions of the trellis decoded DTV signal containing softdecisions as to the symbol-interleaved convolutionally coded ancillarydata are recoded for a Gray-code mapping of symbols to modulationlevels, either before or after symbol de-interleaving, but beforedecoding the outer convolutional coding to recover ancillary data.

In preferred receiver designs soft decisions concerning extrinsicinformation fed back to the ⅔ trellis decoder to close a turbo decodingloop are derived from soft decisions as to the ancillary data. Suchderivation, as performed in accordance with aspects of the invention,includes recoding that cases soft decisions concerning extrinsicinformation to conform to a binary-code mapping of symbols to modulationlevels.

Each of the recoding procedures can be performed using read-only memory,but preferably is performed using simple logic circuitry. In somereceiver designs that embody the invention the recoding is performedusing read-only memory, but in receivers that embody the invention inpreferred forms the recoding is performed using simple logic circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of transmitter apparatus for broadcastdigital television (DTV) signals using serially concatenatedconvolutional coding (SCCC) of M/H type, which transmitter apparatus ismodified in accordance with an aspect of the invention for anti-Graycoding the interleaved outer convolutional coding portion of the SCCC.

FIGS. 2 through 9 are tables of different forms of re-coding that areused in respective embodiments of the DTV transmitter apparatuses ofFIGS. 1 and 10.

FIG. 10 is a general schematic diagram of transmitter apparatus forbroadcast DTV signals using SCCC, which transmitter apparatus embodiesaspects of the invention and anti-Gray codes signaling coding as well asthe interleaved outer convolutional coding portion of the SCCC.

FIG. 11 is a general schematic diagram of receiver apparatus forbroadcast DTV signals using SCCC in which the interleaved outerconvolutional coding is anti-Gray coded, as transmitted by the FIG. 1DTV transmitter apparatus.

FIG. 12 is a general schematic diagram of receiver apparatus forbroadcast DTV signals using SCCC in which the interleaved outerconvolutional coding is anti-Gray coded, as transmitted by the FIG. 10DTV transmitter apparatus.

FIGS. 13, 14, 15 and 16 are schematic diagrams showing variousmodifications that can be made either to the FIG. 11 DTV receiverapparatus or to the FIG. 12 DTV receiver apparatus, which modificationsconcern the way in which extrinsic information is derived for feedingback to the trellis code decoder.

FIG. 17 is a schematic diagrams showing a modification that can be madeeither to the FIG. 11 DTV receiver apparatus or to the FIG. 12 DTVreceiver apparatus, which modification concerns the order in whichde-interleaving and Gray coding are done following the trellis codedecoder.

FIGS. 18, 19, 20 and 21 are schematic diagrams showing variousmodifications that can be made either to the FIG. 17 DTV receiverapparatus, which modifications concern the way in which extrinsicinformation is derived for feeding back to the trellis code decoder.

FIG. 22 is a schematic diagram of a modified block processor thatreplaces the block processor in modified FIG. 1 transmitter apparatusand in modified FIG. 4 transmitter apparatus.

FIG. 23 is a schematic diagram of a modification that can be made to anyof the receiver apparatuses of FIGS. 11 through 21 fitting it to receiveM/H service signals transmitted by the FIG. 1 or FIG. 4 transmitterapparatus as modified to use the FIG. 22 block processor.

FIG. 24 is a schematic diagram of receiver apparatus modified from thoseshown in FIGS. 11 and 12, which FIG. 24 receiver apparatus is suited forreceiving M/H service signals transmitted by the FIG. 1 or FIG. 4transmitter apparatus as modified to use the FIG. 22 block processor.

FIG. 25 is a schematic diagram of modified FIG. 14 receiver apparatussuited for receiving M/H service signals transmitted by the FIG. 1 orFIG. 4 transmitter apparatus as modified to use the FIG. 22 blockprocessor.

FIG. 26 is a schematic diagram of modified FIG. 17 receiver apparatussuited for receiving M/H service signals from the modified transmitterapparatus of FIG. 1 or 4.

FIGS. 27A and 27B are tables showing illustrative contents of read-onlymemory used for recoding symbols from binary-code mapping to Grey-codemapping, or vice versa.

FIG. 28 is a schematic diagram of logic circuitry capable of recodingsymbols from binary-code mapping to Grey-code mapping, or vice versa.

DETAILED DESCRIPTION

A/153 provides broadcasting services for mobile/hand-held (M/H)receivers using a portion of the 19.39 Mbps ATSC 8-VSB transmission,while the remainder is still available for high-definition or multiplestandard-definition television services. The system is a dual-streamsystem: the ATSC service multiplex for existing digital televisionservices and an M/H service multiplex for one or more mobile andhand-held services.

FIG. 1 shows transmitter apparatus for broadcast DTV signals using SCCCof the type prescribed by A/153. The transmitter apparatus receives twosets of input streams: one consists of the MPEG transport stream (TS)packets of the main service data and the other consists of the M/Hservice data. Before being emitted from the transmitter, the M/H servicedata are encapsulated in special MPEG transport packets calledM/H-encapsulating TS packets or MHE packets for short. This is done toavoid disruption of the reception of the main service data for legacy8-VSB receivers. M/H service data can be carried in MPEG transportstreams, such as MPEG-2 video/audio or MPEG-4 video/audio, or can becarried by internet-protocol (IP) packets. The choice of service typescan be made in preceding portions of the transmission system that arenot described in detail in this specification. A primary function of theFIG. 1 transmitter apparatus is to combine these two types of streamsinto one stream of MPEG TS packets and to process the combined streamsfor transmission as an ATSC trellis-coded 8-VSB signal.

M/H Frame controller apparatus 1 controls these procedures. Themain-service multiplex stream of data is supplied to packet timing andPCR adjustment circuitry 2 before the packets of that stream are routedto a packet multiplexer 3 to be time-division multiplexed with packetsencapsulating M/H service data. Because of their time-divisionmultiplexing with the packets encapsulating M/H data, changes have to bemade to the time of emission of the main-service stream packets comparedto the timing that would occur with no M/H stream present. The packettiming and PCR adjustment circuitry 2 makes these timing changesresponsive to control signals supplied thereto from the M/H Framecontroller apparatus 1. The packet multiplexer 3 time-divisionmultiplexes the main-service stream packets with packets encapsulatingM/H service data, as directed by control signals from the M/H Framecontroller apparatus 1. The operations of the M/H transmission system onthe M/H data are divided into two stages: the M/H pre-processor 4 andthe M/H post-processor 5.

The function of the pre-processor 4 is to rearrange the M/H service datainto an M/H data structure, to enhance the robustness of the M/H servicedata by additional FEC processes, to insert training sequences, andsubsequently to encapsulate the processed enhanced data into MPEG nullTS packets. The operations performed by the pre-processor 4 include M/HFrame encoding, block processing, group formatting, packet formattingand M/H signaling encoding. The M/H Frame controller apparatus 1provides the necessary transmission parameters to the pre-processor 4and controls the multiplexing of the main-service data packets and theM/H-service data packets by the packet multiplexer 3 to organize the M/HFrame.

The function of the post-processor 5 is to process the main service databy normal 8-VSB encoding and to manipulate the pre-processed M/H servicedata in the combined stream to ensure backward compatibility with ATSC8-VSB. Main service data in the combined stream are processed exactlythe same way as for normal 8-VSB transmission: randomizing, RS encoding,interleaving and trellis encoding. The M/H service data in the combinedstream are processed differently from the main service data, with thepre-processed MI/H service data bypassing data randomization. Thepre-processed M/H service data is subjected to non-systematic RSencoding. Additional operations are done on the pre-processed M/Hservice data to initialize the trellis encoder memories at the beginningof each training sequence included in the pre-processed M/H servicedata. The non-systematic RS encoding allows the insertion of theregularly spaced long training sequences without disturbing legacyreceivers.

More specifically, the M/H-service multiplex stream of data is suppliedto the M/H pre-processor 4 for processing and subsequent encapsulationin the payload fields of MPEG transport packets with special headersidentifying them as M/H-encapsulating packets. These transport packets,commonly referred to as “MHE packets”, are supplied to the packetmultiplexer 3 after data encapsulation within their payload fields iscompleted.

Still more specifically, the M/H-service multiplex stream of data issupplied to an M/H Frame encoder 6 which provides transverseReed-Solomon (TRS) coding of data packets. The data packets are alsosubjected to periodic cyclic redundancy check (CRC) coding to locatebyte errors for the TRS coding. Each M/H Frame is composed of one or twoframes of the TRS coding, and the data in each frame of the TRS-CRCcoding are randomized independently from each other and from the data ofthe main-service multiplex. The M/H Frame encoder 6 is connected forsupplying packets of M/H-service data and packets of TRS parity byteswithin consecutive blocks of the TRS-CRC two-dimensional coding to ablock processor 7, as input signal thereto. The block processor 7includes encoders for each type of single-phase outer convolutionalcoding used in the SCCC and respective subsequent interleavers forsuccessive 2-bit symbols of each type of single-phase outerconvolutional coding. A read-only memory 8 is connected for receivingthe interleaved outer convolutional coding from the block processor 7 asinput addressing signal.

In accordance with an aspect of the invention, the ROM 8 responds to theinterleaved outer convolutional coding from the block processor 7 withanti-Gray coding of consecutive, contiguous 2-bit symbols thereof. Thisanti-Gray coding is done in accordance with one of the different formsof re-coding shown in the tables of FIGS. 2 through 9. The preferredform of re-coding is that shown in FIG. 2.

The ROM 8 is connected to supply each successive block ofanti-Gray-coded interleaved outer convolutional coding to a groupformatter 9. The group formatter 9 includes an interleaved group formatorganizer that operates on the group format as it will appear after theATSC data interleaver. It maps the FEC coded M/H service data from theblock processor into the corresponding M/H blocks of a group; addspre-determined training data bytes and data bytes to be used forinitializing the trellis encoder memories; and inserts place-holderbytes for main-service data, MPEG-2 header and non-systematic RS parity.The interleaved group format organizer also adds some dummy bytes toconstruct the intended group format. The interleaved group formatorganizer assembles a group of 118 consecutive TS packets. Some of theseTS packets are composed of the anti-Gray-coded interleaved outerconvolutional coding read from the ROM 8. Others of these TS packets areprescribed training signals stored in read-only memory within the groupformatter 9 and inserted at prescribed intervals within the group. Stillothers of these TS packets are generated by a signaling encoder 10.

The M/H transmission system has two kinds of signaling channelsgenerated by the signaling encoder 10. One is the TransmissionParameter. Channel (TPC), and the other is the Fast Information Channel(FIC). The TPC is for signaling the M/H transmission parameters such asvarious FEC modes and M/H Frame information. The FIC is provided toenable the fast service acquisition of receivers and it contains crosslayer information between the physical layer of receivers and theirupper layer(s).

The interleaved group format organizer is followed in cascade connectionby a byte de-interleaver within the group formatter 9. This bytede-interleaver complements the ATSC convolutional byte interleaver. Thegroup formatter 9 is connected for supplying the response of thisde-interleaver as its output signal, which is applied as input signal toa packet formatter 11. Initially, the packet formatter 11 expunges themain service data place holders and the RS parity place holders thatwere inserted by the interleaved Group format organizer for properoperation of the byte de-interleaver in the group formatter 9.Subsequently, the packet formatter 11 replaces the 3-byte MPEG headerplace holder with an MPEG header having an MHE packet PID and inserts anMPEG TS sync byte before each 187-byte data packet as a prefix thereof.The packet formatter 11 supplies 118 MHE TS packets per group to thepacket multiplexer 3, which time-division multiplexes these M/H-serviceTS packets with the main-service TS packets to construct M/H Frames.

The M/H Frame controller apparatus 1 controls the packet multiplexer 3in the following way when the packet multiplexer schedules the 118M/H-service TS packets from the packet formatter 11. Thirty-seven MHEpackets immediately precede a DFS segment in a 313-segment VSB field ofdata, and another eighty-one MHE packets immediately succeed that DFSsegment. The packet multiplexer 3 reproduces next-in-line main-serviceTS packets in place of MPEG null packets that contain place-holder bytesfor main-service data in their payload fields. The packet multiplexer 3is connected to supply the TS packets it reproduces to thepost-processor 5 as input signal thereto.

More specifically, the packet multiplexer 3 is connected to apply the TSpackets it reproduces to a conditional data randomizer 12 as the inputsignal thereto. The conditional data randomizer 12 suppresses the syncbytes of the 188-byte TS packets and randomizes the remaining data inaccordance with conventional 8VSB practice, but only on condition thatit is not encapsulated M/H-service data. The encapsulated M/H-servicedata bypass data randomization. The other remaining data are randomizedper A/53, Annex D, § 4.2.2.

An encoder 13 for systematic and non-systematic (207, 187) Reed-Solomoncodes is connected to receive, as its input signal, the 187-byte packetsthat the conditional data randomizer 12 reproduces with conditional datarandomization. The R-S parity generator polynomial and the primitivefield generator for the Reed-Solomon encoder 13 are the same as thosethat A/53, Annex D, FIG. 5 prescribes for (207, 187) Reed-Solomoncoding. When the R-S encoder 13 receives a main service data packet, theR-S encoder 13 performs the systematic R-S coding process prescribed inA/53, Annex D, § 4.2.3, appending the twenty bytes of R-S parity data tothe conclusion of the 187-byte packet. When the R-S encoder 13 receivesan M/H service data packet, the RS encoder 13 performs a non-systematicRS encoding process. The twenty bytes of R-S parity data obtained fromthe non-systematic RS encoding process are inserted in a prescribedparity byte location within the M/H data packet.

A convolutional byte interleaver 14 is connected for receiving as itsinput signal the 207-byte R-S codewords that the R-S encoder 13generates. The byte interleaver 14 is generally of the type specified inA/53, Annex D, § 4.2.4. The byte interleaver 14 is connected forsupplying byte-interleaved 207-byte R-S codewords via a Reed-Solomonparity replacer 15 to a modified trellis encoder 16. The basic trellisencoding operation of the modified trellis encoder 16 is similar to thatspecified in A/53, Annex D, §4.2.4. The trellis encoder 16 converts thebyte-unit data from the byte interleaver 14 to symbol units and performsa 12-phase trellis coding process per Section 6.4.1.4 Main ServiceTrellis Coding of A53-Part-2-2007. In order for the output data of thetrellis encoder 16 to include pre-defined known training data,initialization of the memories in the trellis encoder 16 is required.This initialization is very likely to cause the R-S parity datacalculated by the R-S encoder 13 prior to the trellis initialization tobe erroneous. The R-S parity data must be replaced to ensure backwardcompatibility with legacy DTV receivers. Accordingly, the trellisencoder is connected for supplying the changed initialization byte to anencoder 17 for non-systematic (207, 187) Reed-Solomon codes, whichencoder 17 re-calculates the RS parity of the affected M/H packets. Theencoder 17 is connected for supplying the re-calculated R-S parity bytesto the R-S parity replacer 15, which substitutes the re-calculated R-Sparity bytes for the original R-S parity bytes before they can besupplied to the modified trellis encoder 16. That is, the R-S parityreplacer 15 reproduces the output of the byte interleaver 14 as the databytes for each packet in its output signal, but reproduces the output ofthe non-systematic R-S encoder 17 as the R-S parity for each packet inits output signal. The R-S parity replacer 15 is connected to supply theresulting packets in its output signal to the modified trellis encoder16 as the input signal thereto.

A synchronization multiplexer 18 is connected for receiving as the firstof its two input signals the ⅔ trellis-coded data generated by themodified trellis encoder 16. The sync multiplexer 18 is connected forreceiving its second input signal from a generator 19 of synchronizationsignals comprising the data segment sync (DSS) and the data field sync(DFS) signals. The DSS and DFS are time-division multiplexed with the ⅔trellis-coded data per custom in the output signal from the syncmultiplexer 18, which is supplied to a pilot inserter 20 as input signalthereto. The pilot inserter 20 introduces a direct component offset intothe signal for the purpose of generating a pilot carrier wave duringsubsequent balanced modulation of a suppressed intermediate-frequency(IF) carrier wave. The output signal from the pilot inserter 20 is amodulating signal, which may be passed through a pre-equalizer filter 21before being supplied as input signal to an 8-VSB exciter 22 to modulatethe suppressed IF carrier wave. The 8-VSB exciter 22 is connected forsupplying the suppressed IF carrier wave to a radio-frequencyup-converter 23 to be converted upward in frequency to repose within thebroadcast channel. The upconverter 23 also amplifies the power of theradio-frequency (RF) signal that it applies to the broadcast antenna 24.

FIG. 10 shows transmitter apparatus for broadcast DTV signals usingSCCC, which FIG. 10 transmitter apparatus differs from the FIG. 1transmitter apparatus in that signaling coding is anti-Gray coded aswell as the interleaved outer convolutional coding portion of the SCCC.The M/H pre-processor 4 of the FIG. 1 transmitter apparatus is replacedby an M/H pre-processor 4′ in the FIG. 2 transmitter apparatus. In theM/H pre-processor 4′ the interleaved outer convolutional coding from theblock processor 7 is supplied directly to the group formatter 9 as inputsignal thereto. The connection from the block processor 7 to the groupformatter 9 omits the ROM 8 used in the M/H pre-processor 4 of the FIG.1 transmitter apparatus. In the M/H pre-processor 4′ the output signalfrom the group formatter 9 is supplied to a read-only memory 25 as inputaddressing signal thereto. The ROM 25 responds to the output signal fromthe group formatter 9 with anti-Gray coding of consecutive, contiguous2-bit symbols thereof. This anti-Gray coding is done in accordance withone of the different forms of re-coding shown in the tables of FIGS. 2through 9. The preferred form of re-coding is that shown in FIG. 2.

FIG. 11 shows receiver apparatus for M/H signals transmitted by M/Htransmitter apparatus of the sort shown in FIG. 1. The FIG. 11 receiverapparatus includes a vestigial-sideband amplitude-modulation (VSB AM)DTV receiver front-end 26 for selecting a radio-frequency DTV signal forreception, converting the selected RF DTV signal to anintermediate-frequency DTV signal, and for amplifying the IF DTV signal.An analog-to-digital converter 27 is connected for digitizing theamplified IF DTV signal supplied from the DTV receiver front-end 26. Ademodulator 28 is connected for demodulating the digitized VSB AM IF DTVsignal to generate a digitized baseband DTV signal, which is supplied todigital filtering 29 for equalization of channel response and forrejection of co-channel interfering NTSC signal. Sync extractioncircuitry 30 is connected for receiving the digital filtering 29response and extracting synchronization signals. Responsive todata-field-synchronization (DFS) signals, the sync extraction circuitry30 detects the beginnings of data frames and fields. Responsive todata-segment-synchronization (DSS) signals, the sync extractioncircuitry 30 detects the beginnings of data segments. The FIG. 11 DTVreceiver apparatus uses the DSS and DFS signals for controlling itsoperations similarly to the way this is conventionally done in DTVreceivers. FIG. 11 does not explicitly show the circuitry for effectingthese operations.

A decoder 31 for detecting the type of ancillary transmission respondsto 8-bit sequences contained in final portions of the reserved portionsof DFS signals separated by the sync extraction circuitry 30. Thedecoder 31 is connected for indicating the type of ancillarytransmission to turbo decoding control circuitry 32 that controls turbodecoding in the FIG. 11 DTV receiver apparatus. The type of ancillarytransmission that the decoder 31 detects conditions it to extractfurther information concerning the ancillary transmission from theinitial portions of the reserved portions of DFS signals separated bythe sync extraction circuitry 30. The decoder 31 is connected forsupplying this further information to the turbo decoding controlcircuitry 32. This further information includes pointers to portions ofthe data field that contain signaling information describing ancillarytransmission in greater detail.

FIG. 11 shows a 12-phase trellis decoder 33 connected for receiving thedigital filtering 29 response. In actual practice the 12-phase trellisdecoder 33 shown in FIG. 11 is apt to be a plurality of component12-phase trellis decoders, each capable of decoding the digitalfiltering 29 response. Such construction of the trellis decoder 33facilitates turbo decoding of various types of SCCC being carried onindependently of each other, each using separate temporary storage ofdata and a respective decoder for each type of outer convolutionalcoding. Each component decoder within the 12-phase trellis decoder 33 isa respective soft-input/soft-output (SISO) inner decoder within a turbodecoding loop.

FIG. 11 further shows the 12-phase trellis decoder 33 connected forsupplying trellis-decoding results to a signaling decoder 34. In actualpractice, these trellis-decoding results may be supplied by one of aplurality of component 12-phase trellis decoders in the trellis decoder33, and the signaling decoder 34 may be connected to feed back extrinsicinformation to that component trellis decoder to implement turbodecoding. The component 12-phase trellis decoder will include memory forstoring the digital filtering 29 response for updating by the extrinsicinformation. The turbo decoding control circuitry 32 enables operationof the signaling decoder 34 during those portions of the data field thatcontain signaling information describing ancillary transmission ingreater detail. To keep FIG. 11 from being too cluttered to beunderstood readily, FIG. 11 does not explicitly show most of theconnections of the turbo decoding control circuitry 32 to the elementsinvolved in decoding the SCCC.

FIG. 11 shows the 12-phase trellis decoder 33 further connected forsupplying trellis-decoding results to a byte de-interleaver 35. Inactual practice, these trellis-decoding results may be supplied by oneof a plurality of component 12-phase trellis decoders in the trellisdecoder 33. The byte de-interleaver 35 provides byte-by-bytede-interleaving of these results to generate input signal for aReed-Solomon decoder 36 of the de-interleaved (207, 187) R-S FECcodewords supplied from the de-interleaver 35. Preferably, thede-interleaved (207, 187) R-S FEC codewords are accompanied bysoft-decision information, and the R-S decoder 36 is of a sort that canuse the soft-decision information to improve overall performance of thedecoders 33 and 36. The R-S decoder 36 is connected for supplyingpackets of randomized hard-decision data to a data de-randomizer 37,which exclusive-ORs the bits of the randomized hard-decision data withappropriate portions of the PRBS prescribed in A/53, Annex D, §4.2.2 togenerate a first transport stream. This first transport stream isconstituted in part of MPEG-2-compatible packets of de-randomizedprincipal data. Insofar as the R-S decoder 36 is capable, it correctsthe hard-decision 187-byte randomized data packets that it supplies tothe data de-randomizer 37. The output signal from the data de-randomizer37 reproduces the main-service multiplex transport stream. Receiversintended for just the reception of M/H service data will omit the bytede-interleaver 35, the R-S decoder 36 and the data de-randomizer 37.

FIG. 11 shows the 12-phase trellis decoder 33 further connected as asoft-input, soft-output (SISO) inner decoder in a turbo decoding loopthat also includes a soft-input, soft-output (SISO) outer decoder 38. Inactual practice, another of a plurality of component 12-phase trellisdecoders in the trellis decoder 33 is connected to function as the SISOinner decoder in this turbo decoding loop. Then, the outer SISO decoder38 is connected to feed back extrinsic information to that componenttrellis decoder to implement turbo decoding. The turbo decodingprocedures often involve iterations of both decoding of the innerconvolutional code of the SCCC by the SISO trellis decoder 33 anddecoding of the outer convolutional code of the SCCC by the outer SISOdecoder 38. The component 12-phase trellis decoder will include memoryfor storing the digital filtering 29 response for updating by theextrinsic information. The decoding operations of the decoders 33 and 38are staggered in time. The decoders 33 and 38 may be of types that usethe soft-output Viterbi algorithm (SOVA) for evaluating code trellises,but preferably are of types that use the logarithmic maximum aposteriori algorithm (log-MAP) for such evaluations. In any case, bothof the decoders 33 and 38 comprise memory for temporary storage of thesoft-decisions that they respectively generate.

Input/output circuitry 39 is used for accessing selected portions of thememory in the trellis decoder 33 for temporary storage of soft-decisionsrelated to the inner convolutional coding and to the symbol-interleavedouter convolutional coding of the SCCC. This input/output circuitry 39includes a memory address generator, the operation of which iscontrolled by the turbo code decoding control circuitry 32. Responsiveto control by the turbo code decoding control circuitry 32, theinput/output circuitry 39 reads soft-decisions related to the reproducedanti-Gray-coded interleaved outer convolutional coding of the SCCC tothe cascade connection of a read-only memory 40 and a symbolde-interleaver 41. The input/output circuitry 39 also reads thosesoft-decisions another, later time to a comparator unit 42 as one of itsinput signals. The cascade connection of the ROM 40 and the symbolde-interleaver 41 is collectively referred to as a data processor in theclaims appended to this specification.

In accordance with an aspect of the invention, the ROM 40 is connectedfor recoding the soft decisions related to the reproducedsymbol-interleaved and anti-Gray-coded outer convolutional coding of theSCCC such that they appear to have originated from the use of a symbolmap for Gray-coded modulation rather than from a symbol map forbinary-coded modulation. Presuming the soft decisions consist of twosoft bits, each soft bit expressed in logarithmic likelihood ratio (LLR)or similar format, this recoding procedure may be loosely referred to asa Gray coding procedure on the soft bits. The de-interleaver 41 iscomplementary to an interleaver in the block processor 7 of the FIG. 1or FIG. 10 transmitter apparatus, which interleaver performsinterleaving 2-bit symbol by 2-bit symbol. The de-interleaver 41 isconnected for de-interleaving the symbol-interleaved outer convolutionalcoding of the SCCC 2-soft-bit symbol by 2-soft-bit symbol and supplyingthe resulting de-interleaved outer convolutional coding to the outerSISO decoder 38 as “soft” input signal thereto. The de-interleaver 41 iscustomarily constructed from random-access memory (RAM) written withwrite addressing different from its read addressing when subsequentlyread. The outer SISO decoder 38 is connected for supplying softdecisions concerning its decoding results to an interleaver 43 thatinterleaves the soft decisions to generate input addressing for aread-only memory 44. The pattern of 2-soft-bit symbol by 2-soft-bitsymbol interleaving by the interleaver 43 corresponds to the 2-bitsymbol by 2-bit symbol interleaving by the interleaver in the blockprocessor 7 of the FIG. 1 or FIG. 4 transmitter apparatus.

The ROM 44 responds to input addressing from the interleaver 43 tosupply soft decisions that are recoded to the anti-Gray coding regimeassociated with the use of a symbol map for binary-coded modulationrather than from a symbol map for Gray-coded modulation. The comparatorunit 42 for determining extrinsic information feedback is connected forreceiving the interleaved soft decisions in the anti-Gray coding regimethat the trellis decoder 33 and the ROM 44 respectively supply as theiroutput signals. The comparator unit 42 contains memory for temporarilystoring the soft decisions supplied from the trellis coder 33 until softdecisions are subsequently supplied from the SISO decoder 38 via theinterleaver 43 and the anti-Gray coding ROM 44. The comparator unit 42then compares the two sets of soft decisions for determining extrinsicinformation. This extrinsic information is coded in accordance with theanti-Gray coding regime associated with the use of a symbol map forbinary-coded modulation rather than from a symbol map for Gray-codedmodulation. So, this extrinsic information is appropriate for closingthe turbo decoding loop by being fed back via the I/O circuitry 39 tomemory within the trellis decoder 33 for updating stored soft-inputdata. The stored soft input data as so updated will be used by thetrellis decoder 33 in any iteration of its decoding procedure. Thisextrinsic information is also used to modify the soft decisions that theI/O circuitry 39 supplies to the data processor comprising the cascadeconnection of the ROM 40 and the symbol de-interleaver 41.

FIG. 11 shows the SISO decoder 38 connected for supplying its softdecisions to hard-decision circuitry 45, which generates hard decisionsto the soft decisions supplied thereto. The hard-decision circuitry 45is connected to supply the resulting hard decisions as to the randomizeddata to an M/H frame decoder 46 as input signal thereto. The M/H Framedecoder 46 includes decoders for RS Frames, which FIG. 11 does notexplicitly show. Hard decisions related to each RS Frame are collectedinto bytes that are written into rows of byte storage locations in arespective byte-organized framestore memory. Each row of bytes writteninto the framestore memory includes a checksum forcyclic-redundancy-check (CRC) coding, and each column of those bytes isa transversal Reed-Solomon codeword that is decoded using abyte-error-correcting algorithm that employs the CRC coding as anerror-locating code. The M/H Frame decoder 46 is connected for supplyingits output signal to a bank 47 of data de-randomizers as their inputsignals, each decoder for an RS Frame having a respective datade-randomizer. The turbo decoding control circuitry 32 is connected forsupplying a control signal that selects the response of one of the bank47 of data de-randomizers that is suitable for reproducing theM/H-service multiplex transport stream.

FIG. 12 shows receiver apparatus for M/H signals transmitted by M/Htransmitter apparatus of the sort shown in FIG. 10. The principaldifference from the FIG. 1 receiver apparatus is that the signalingdecoder 34 is not connected to receive its input signal directly fromthe decoder 33 for 12-phase trellis codes. Instead, the signalingdecoder 34 is connected to receive its input signal read from aread-only memory 48 addressed by output signal from the decoder 33. TheROM 48 is similar to the ROM 40 and, like ROM 40, Gray codes the softdecisions related to the reproduced anti-Gray-coded (interleaved) outerconvolutional coding of the SCCC.

FIG. 13 shows a modification that can be made to the receiverapparatuses of FIGS. 11 and 12. FIG. 13 shows the positions of thesymbol interleaver 43 and the ROM 44 in their cascade connection havingbeen interchanged, such that the ROM 44 precedes the interleaver 43within the data processor linking the I/O circuitry 39 to the outer SISOdecoder 38.

FIG. 14 shows a different modification of the FIG. 11 and FIG. 12receiver apparatuses that provides further receiver apparatusesembodying the invention. The comparator unit 42 for determiningde-interleaved extrinsic information and the ROM 44 for recodinginterleaved soft decisions to the anti-Gray coding regime are replaced.FIG. 14 shows a comparator unit 48 for determining Gray-coded extrinsicinformation, which comparator unit 48 is connected for comparing theresponse from the ROM 40 with the response from the symbol interleaver43 for soft decisions from the SISO decoder 38. A read-only memory 49 isconnected to receive the Gray-coded extrinsic information as its inputaddressing. The ROM 49 responds to supply extrinsic information that isrecoded to the anti-Gray coding regime. ROM 49 is connected forsupplying that extrinsic information to the I/O circuitry 39 used foraccessing selected portions of the memory in the trellis decoder 33,which connection closes the turbo decoding loop for the FIG. 14 DTVreceiver. This extrinsic information will be used by the trellis decoder33 in any iterative turbo decoding procedure that it performs.

FIGS. 15 and 16 show still other possible modifications of the FIG. 11and FIG. 12 receiver apparatuses. The comparator unit 42 for determiningde-interleaved extrinsic information, the symbol interleaver 43 forinterleaving soft decisions, and the ROM 44 for recoding interleavedsoft decisions to the anti-Gray coding regime are replaced in both FIGS.15 and 16. In both FIGS. 15 and 16 a comparator unit 50 for determiningde-interleaved Gray-coded extrinsic information is connected forcomparing the soft-decision output signal from the SISO decoder 38 withthe “soft” input signal to the SISO decoder 38.

In FIG. 15 a symbol interleaver 51 is connected for receivingtwo-soft-bit symbols of de-interleaved Gray-coded extrinsic informationfrom the comparator unit 50 and re-interleaving them to supply inputaddressing to the read-only memory 49. The ROM 49 responds to supplyextrinsic information that is recoded to the anti-Gray coding regimeassociated with the use of a symbol map for binary-coded modulationrather than from a symbol map for Gray-coded modulation. ROM 49 isconnected for supplying that extrinsic information to the input/outputcircuitry 39 used for accessing selected portions of the memory in thetrellis decoder 33, which connection closes the turbo decoding loop forthe FIG. 15 DTV receiver. This extrinsic information will be used by thetrellis decoder 33 in any iterative turbo decoding procedure that itperforms.

In FIG. 16 the ROM 49 is connected for receiving two-bit symbols ofde-interleaved Gray-coded extrinsic information from the comparator unit50 as input addressing. The ROM 49 responds to supply de-interleavedextrinsic information that is recoded to the anti-Gray coding regimeassociated with the use of a symbol map for binary-coded modulationrather than from a symbol map for Gray-coded modulation. The symbolinterleaver 51 is connected for receiving two-soft-bit symbols of thede-interleaved extrinsic information that has been recoded to theanti-Gray coding regime and for supplying re-interleaved extrinsicinformation to the input/output circuitry 39 used for accessing selectedportions of the memory in the trellis decoder 33, which connectioncloses the turbo decoding loop for the FIG. 16 DTV receiver. Thisextrinsic information will be used by the trellis decoder 33 in anyiterative turbo decoding procedure that it performs.

FIG. 17 shows another modification that can be made to the receiverapparatuses of FIGS. 11 and 12, which modification affects the dataprocessor comprising the symbol de-interleaver 41 and the ROM 40 incascade connection. FIG. 17 shows the positions of the symbolde-interleaver 41 and the ROM 40 in their cascade connection having beeninterchanged, such that the de-interleaver 41 precedes the ROM 40.

FIG. 18 shows a modification that can be made to the FIG. 13 receiverapparatus, which modification affects the data processor comprising thesymbol de-interleaver 41 and the ROM 40 in cascade connection. FIG. 18shows the positions of the symbol de-interleaver 41 and the ROM 40 intheir cascade connection having been interchanged, such that thede-interleaver 41 precedes the ROM 40.

FIG. 19 shows a different modification of the FIG. 17 receiver apparatusthat provides further receiver apparatuses that embody the invention.FIG. 19 shows the ROM 44 being connected for receiving its inputaddressing directly from the SISO decoder 38 as in FIGS. 17 and 18. Theresponse from the ROM 44 recodes the de-interleaved soft decisions tothe anti-Gray coding regime associated with the use of a symbol map forbinary-coded modulation rather than from a symbol map for Gray-codedmodulation. The comparator unit 42 for determining de-interleavedextrinsic information and the interleaver 43 for soft decisions of FIGS.17 and 18 are replaced in FIG. 19 by a comparator unit 52 fordetermining de-interleaved extrinsic information and the symbolinterleaver 51 for re-interleaving two-soft-bit symbols of thede-interleaved extrinsic information. The ROM 44 is further connectedfor supplying the recoded de-interleaved soft decisions to thecomparator unit 52 for determining de-interleaved extrinsic information,as one of two input signals thereto. The response of the symbolde-interleaver 41 for soft decisions from the I/O circuitry 39 isapplied to the comparator unit 52 as the other input signal thereto. Thecomparator unit 52 is connected for supplying de-interleaved extrinsicinformation to the symbol interleaver 51. The symbol interleaver 51interleaves the successive 2-soft-bit symbols of extrinsic informationfor application to the input/output circuitry 39 used for accessingselected portions of the memory in the trellis decoder 33, whichconnection closes the turbo decoding loop for the FIG. 19 DTV receiver.This extrinsic information will be used by the trellis decoder 33 in anyiterative turbo decoding procedure that it performs.

FIG. 20 shows a modification that can be made to the FIG. 15 receiverapparatus, which modification affects the data processor comprising thesymbol de-interleaver 41 and the ROM 40 in cascade connection. FIG. 20shows the positions of the symbol de-interleaver 41 and the ROM 40 intheir cascade connection having been interchanged, such that thede-interleaver 41 precedes the ROM 40.

FIG. 21 shows a modification that can be made to the FIG. 16 receiverapparatus which modification affects the data processor comprising thesymbol de-interleaver 41 and the ROM 40 in cascade connection. FIG. 21shows the positions of the symbol de-interleaver 41 and the ROM 40 intheir cascade connection having been interchanged, such that thede-interleaver 41 precedes the ROM 40.

FIG. 22 shows a block processor 70 comprising elements 71-79 that mayreplace the block processor 7 in the FIG. 1 DTV transmitter apparatus orin the FIG. 4 transmitter apparatus. The M/H frame encoder 6 isconnected for supplying sub-frames of RS Frames in 8-bit byte format asinput signal to a byte-to-serial-bit format converter 71. The formatconverter 71 is connected for supplying the M/H frame encoder 6 responseas converted to serial-bit format to a bit de-interleaver 72 within theblock processor 70. The bit de-interleaver 72 is a block de-interleaverthat de-interleaves the bits of each successive block so as tocomplement the symbol interleaving that will follow outer convolutionalcoding. The bit de-interleaver 72 is connected to supply the M/H frameencoder 6 response after bit-by-bit de-interleaving to encoders 73, 74and 75 as their respective input signals. The encoders 73, 74 and 75shown in FIG. 22 generate one-half-rate outer convolutional coding,one-third-rate outer convolutional coding and one-quarter-rate outerconvolutional coding, respectively.

FIG. 22 shows apparatus 76 for selectively enabling operation of theencoders 73, 74 and 75 one at a time. If the encoders 73, 74 and 75 haveseparate physical structures, the apparatus 76 for selectively enablingoperation can by way of example be such as to supply operating powerjust to a selected one of the three encoders. In actual practice theencoders 73, 74 and 75 will probably use elements in common. In suchcase the apparatus 76 will comprise selective connection circuitry forselecting the outer convolutional coding with desired rate. FIG. 22shows the encoders 73, 74 and 75 connected for supplying serial two-bitsymbols to an output bus 77 for subsequent application to a symbolinterleaver 78. In modified FIG. 1 transmitter apparatus the symbolinterleaver 78 is connected for supplying the interleaved two-bitsymbols to the anti-Gray coder ROM 8. In modified FIG. 4 transmitterapparatus the symbol interleaver 78 is connected for supplying theinterleaved two-bit symbols to the M/H Group formatter 9.

FIG. 23 is a schematic diagram of a modification that can be made to anyof the receiver apparatuses of FIGS. 11 through 21 fitting it to receiveM/H service signals transmitted by the modified FIG. 1 transmitterapparatus or the modified FIG. 4 transmitter apparatus. In the FIG. 23modification the M/H Frame decoder 46 is not supplied the response ofthe hard-decision unit 45 directly. Instead, the response of thehard-decision unit 45 is applied as input signal to a bit interleaver55. The bit interleaver 55 is connected to supply its response as inputsignal to the M/H Frame decoder 46. In the bit interleaver 55 responsethe order of bits from the hard-decision unit 45 response are shuffledto compensate for the preliminary de-interleaving of bits by the bitde-interleaver 72 in the block processor 70 of modified FIG. 1 or FIG. 4transmitter apparatus. The need for the bit de-interleaver 55 followingthe hard-decision unit 45 can be avoided in modifications of certain ofthe receiver apparatuses thusfar described. Changing the point in theturbo-decoding loop from which input signal for the hard-decision unit45 is taken accomplishes this.

FIG. 24 is a schematic diagram of receiver apparatus modified from thoseshown in FIGS. 11 and 12, which FIG. 24 receiver apparatus is suited forreceiving M/H service signals from the transmitter apparatus of FIG. 1or 4 as modified to use the FIG. 22 block processor. The hard-decisionunit 45 is connected for receiving input signal supplied as responsefrom the symbol interleaver 43 for soft decisions from the SISO decoder38. This avoids the need for the bit de-interleaver 55 following thehard-decision unit 45 in order to compensate for the preliminaryde-interleaving of bits by the bit de-interleaver 72 in the blockprocessor 70 of modified FIG. 1 or FIG. 4 transmitter apparatus.

FIG. 25 is a schematic diagram of modified FIG. 14 receiver apparatussuited for receiving M/H service signals from the transmitter apparatusof FIG. 1 or 4 as modified to use the FIG. 22 block processor. Thehard-decision unit 45 is connected for receiving input signal suppliedas response from the symbol interleaver 43, avoiding the need for thebit de-interleaver 55 following the hard-decision unit 45.

FIG. 26 is a schematic diagram of modified FIG. 17 receiver apparatussuited for receiving M/H service signals from the transmitter apparatusof FIG. 1 or 4 as modified to use the FIG. 22 block processor. Thehard-decision unit 45 is connected for receiving input signal suppliedas response from the symbol interleaver 43, avoiding the need for thebit de-interleaver 55 following the hard-decision unit 45.

The interleaver in the block processor of an M/H type of transmitterapparatus (e.g., in the block processor 7 of the FIG. 1 or FIG. 4transmitter apparatus) provides 2-bit symbol by 2-bit symbolinterleaving prior to anti-Gray coding. In the receiver apparatusesshown in FIGS. 17-22, 25 and 26 the de-interleaver 41 is connected afterthe ROM 40 for Gray coding soft decisions from the trellis decoder 33.If only receiver apparatuses of the sort shown in FIGS. 17-22, 25 and 26are used, the de-interleaver 41 and the interleaver in the blockprocessor of the transmitter apparatus could be alternatively designedto implement bit-by-bit interleaving, rather than symbol-by-symbolinterleaving. In the receiver apparatuses shown in FIGS. 17-22, 25 and26 the de-interleaver 41 is connected before the ROM 40 for Gray codingsoft decisions from the trellis decoder 33. Therefore, thede-interleaver 41 must provide 2-bit symbol by 2-bit symbolde-interleaving to preserve the relationship of the two soft bits ineach soft decision regarding a respective symbol. Preservation of thisrelationship is essential for correct input addressing of the ROM 40.

In an alternative design of the DTV transmitter apparatus the anti-Graycoding precedes 2-bit symbol by 2-bit symbol interleaving. If onlyreceiver apparatuses of the sort shown in FIGS. 17-22, 25 and 26 areused, the de-interleaver in the receiver and the interleaver in theblock processor of this alternative-design transmitter apparatus couldbe modified to implement bit-by-bit interleaving. In the receiverapparatuses shown in FIGS. 17-22, 25 and 26 modification of theinterleaver in the block processor of this alternative-designtransmitter apparatus would disrupt the relationship of the two softbits in each soft decision used for addressing the ROM 40, however.

If the SCCC employs 2-bit symbol by 2-bit symbol interleaving, the orderin which the interleaving and anti-Gray coding of the 2-bit symbols isperformed in the transmitter is of no appreciable consequence. Receiverapparatuses of the sort shown in FIGS. 17-22, 25 and 26 in which thesymbol de-interleaver 41 precedes the ROM 40 for recoding soft decisionshave the advantage that symbol de-interleaving can use random-accessmemory that is already included within the inner SISO decoder 33 in mostdesigns. Symbol de-interleaving can be implemented simply by applyingappropriate read addressing to this memory. The FIG. 17 and FIG. 26receiver apparatuses have the further advantage that the symbolinterleaver 43 can use random-access memory that is already includedwithin the outer SISO decoder 38 in most designs. Symbol interleavingcan be implemented simply by applying appropriate read addressing tothis memory.

FIGS. 27A and 27B are tables illustrating the nature of the contents ofread-only memory used for recoding symbols from binary-code mapping toGrey-code mapping, or vice versa. The recoding is performed inaccordance with recoding table 1 shown in FIG. 2. The recoder ROM usedfor this illustration has 6-bit-wide input addressing of sixty-fouraddressed storage locations, each storing a respective 6-bit-wideresponse. Each 6-bit-wide input address is composed of two “soft” bits,each consisting of a respective set of three bits, the initial bit beinga “hard” bit and the final two bits expressing the probability of thepreceding “hard” bit being correct. The highest probability of a ZERO“hard” bit being correct is expressed by the final bits being 00. Asmaller probability of the ZERO “hard” bit being correct is expressed bythe final bits being 01. A still smaller probability of the ZERO “hard”bit being correct is expressed by the final bits being 10. The smallestprobability of the ZERO “hard” bit being correct is expressed by thefinal bits being 11. The smallest probability of a ONE “hard” bit beingcorrect is expressed by the final bits being 00. A larger probability ofthe ONE “hard” bit being correct is expressed by the final bits being01. A still larger probability of the ONE “hard” bit being correct isexpressed by the final bits being 10. The highest probability of the ONE“hard” bit being correct is expressed by the final bits being 11. Each6-bit-wide response stored in the recoder ROM is composed of two “soft”bits, each consisting of a respective set of three bits, the initial bitbeing a “hard” bit and the final two bits expressing the probability ofthe preceding “hard” bit being correct. The final two bits express theprobability of the preceding “hard” bit being correct in each “soft” bitof the response of the recoder ROM in the same way as in each “soft” bitof the input address of the recoder ROM.

The inventor made the following observations from the recoder ROMcontents tabulated in FIGS. 27A and 27B. The initial one of the two softbits of the response supplied from the recoder ROM is identical to theinitial one of the two soft bits of the input address supplied to therecoder ROM. If the “hard” bit of the initial soft bit of the inputaddress supplied to the recoder ROM is a ZERO, the final one of the twosoft bits of the response from the recoder ROM is identical to the finalone of the two soft bits of its input address. If the “hard” bit of theinitial soft bit of the input address supplied to the recoder ROM is aONE, however, the final soft bit of the response from the recoder ROMones-complements the final soft bit of its input address. Theseobservations led the inventor to investigate whether logic circuitrymight be used to replace the recoder ROM. The inventor speculated thatlogic circuitry might usefully replace the more sizable recoder ROMslikely to be needed in actual practice, in which soft bits consisting ofas many as eight or so simple bits were likely to be required.

FIG. 28 shows simple logic circuitry that can be used instead of ROM forrecoding 2-soft-bit symbols from a mapping for binary-code modulation toa mapping for reflected-binary-code modulation—i.e., for Gray-codemodulation—or vice versa. Each of the soft bits in the 2-soft-bitsymbols of both the binary and reflected-binary codes is presumed toconsist of eight bits altogether, which presumption is consisted withwhat is expected to be used in actual practice. The two “hard” bits inthe 2-soft-bit symbols of the reflected-binary code are presumed to bethose for the preferred type of recoding tabulated in FIG. 2.Positive-going amplitude modulation of the 8VSB AM signal is associatedwith the recoded Z-sub-2 “hard” bit being a logic ONE, andnegative-going amplitude modulation of the 8VSB AM signal is associatedwith the recoded Z-sub-2 bit “hard” being a logic ZERO. Irrespective ofthe sense of modulation, lesser amplitude modulation of the 8VSB AMsignal is associated with the recoded Z-sub-1 “hard” bit being a logicONE, and greater amplitude modulation of the 8VSB AM signal isassociated with the recoded Z-sub-1 “hard” bit being a logic ZERO. Theremaining bits of each soft bit express the probability of the preceding“hard” bit being correct using an expansion of the scheme described inconnection with FIGS. 27A and 27B.

The initial one of the two soft bits in the symbol supplied to therecoder 60 shown in FIG. 28, is passed through the recoder 60 withoutchange to provide the initial one of the two soft bits in a respectivesymbol of the recoder 60 response. Each of the component eight simplebits in the final one of the two soft bits in the symbol supplied to therecoder 60 is supplied to a first of two input connections of arespective one of exclusive-OR gates 61, 62, 63, 64, 65, 66, 67 and 68included within the recoder 60. The component bit of the initial one ofthe two soft bits in the symbol supplied to the recoder 60 that isvariously referred to as its sign bit or “hard” bit is applied to therespective second input connections of the exclusive-OR gates 61, 62,63, 64, 65, 66, 67 and 68. The final one of the two soft bits in eachsymbol of the recoder 60 response is supplied from via outputconnections from the exclusive-OR gates 61, 62, 63, 64, 65, 66, 67 and68.

In practice, alternative constructions of the receivers shown in FIGS.11-21 and 24-26 are preferred, which alternative constructions replacethe ROM 40 with a recoder constructed per FIG. 28. Preferably, suchalternative constructions of the receivers shown in FIGS. 11-13, 17, 18,24 and 26 also replace the ROM 44 with another recoder constructed perFIG. 28. Preferably, such alternative constructions of the receiversshown in FIGS. 14, 15, 16, 20, 21 and 25 also replace the ROM 49 withanother recoder constructed per FIG. 28.

FIG. 28 shows a recoder 80 composed of simple logic circuitry, which isdesigned for recoding as tabulated in FIG. 3. Positive-going amplitudemodulation of the 8VSB AM signal is associated with the recoded Z-sub-2“hard” bit being a logic ONE, and negative-going amplitude modulation ofthe 8VSB AM signal is associated with the recoded Z-sub-2 bit “hard”being a logic ZERO. Irrespective of the sense of modulation, lesseramplitude modulation of the 8VSB AM signal is associated with therecoded Z-sub-1 “hard” bit being a logic ZERO, and greater amplitudemodulation of the 8VSB AM signal is associated with the recoded Z-sub-1“hard” bit being a logic ONE. The remaining bits of each soft bitexpress the probability of the preceding “hard” bit being correct. Arecoder constructed similarly to the recoder 80 can be used instead ofthe ROM 40 for recoding 2-soft-bit symbols from a mapping forbinary-code modulation to a mapping for reflected-binary-codemodulation. A recoder constructed similarly to the recoder 80 can beused for recoding 2-soft-bit symbols from a mapping forreflected-binary-code modulation to a mapping for binary-codemodulation, rather than using the ROM 44 or the ROM 49.

The initial one of the two soft bits in the symbol supplied to therecoder 80 shown in FIG. 29, is passed through the recoder 80 withoutchange to provide the initial one of the two soft bits in a respectivesymbol of the recoder 80 response. Each of the component eight simplebits in the final one of the two soft bits in the symbol supplied to therecoder 80 is supplied to a first of two input connections of arespective one of exclusive-NOR gates 81, 82, 83, 84, 85, 86, 87 and 88included within the recoder 80. The component bit of the initial one ofthe two soft bits in the symbol supplied to the recoder 80 that isvariously referred to as its sign bit or “hard” bit is applied to therespective second input connections of the exclusive-NOR gates 81, 82,83, 84, 85, 86, 87 and 88. The final one of the two soft bits in eachsymbol of the recoder 80 response is supplied from via outputconnections from the exclusive-NOR gates 81, 82, 83, 84, 85, 86, 87 and88.

The recoder 60 can be used for recoding as tabulated in FIG. 4. Thepositions of the soft bits in each symbol are interchanged in the inputsignal before applying it to the recoder 60 for recoding per the FIG. 4tabulation. The recoder 80 can be used for recoding as tabulated in FIG.5. The positions of the soft bits in each symbol are interchanged in theinput signal before applying it to the recoder 80 for recoding per theFIG. 5 tabulation. Digital logic circuitry can be devised for recodingas tabulated in each of FIGS. 6, 7, 8 and 9, but will be more complexthan the described digital logic circuitry for recoding as tabulated ineach of FIGS. 2, 3, 4 and 5.

Considerable amounts of any one of the receiver apparatuses describedsupra may be constructed using integrated circuitry comprising suitablyprogrammed microcomputer circuitry that is the operating equivalent ofthe structures shown in that receiver apparatus. Accordingly, the claimswhich follow, although directed to structures employing special-purposecircuit elements in order to further definiteness in claiming, should beinterpreted to include within their scope of protection those structuresemploying general-purpose circuit elements that are operatingequivalents.

In the claims which follow, the word “said” rather than the word “the”is used to indicate the existence of an antecedent basis for a termhaving being provided earlier in the claims. The word “the” is used forpurposes other than to indicate the existence of an antecedent basis fora term having being provided earlier in the claims, the usage of theword “the” for other purposes being consistent with normal grammar inthe American English language.

1. (canceled)
 2. A receiver for vestigial-sideband amplitude-modulation(VSB AM) signal, successive symbols of the modulating signal for saidVSB AM signal defining a digital signal in accordance with aneight-level symbol alphabet superposed on a pedestal, said digitalsignal composed of successive frames each composed of two respectivefields of digital-signal symbols, each said field composed of arespective initial segment of 832 digital-signal symbols succeeded byrespective 312 consecutive further segments of 832 digital-signalsymbols apiece, the four initial digital-signal symbols of each of saidsegments of 832 digital-signal symbols being a prescribed data segmentsynchronizing signal sequence, the final 828 digital-signal symbols ofsaid 312 further segments of each said field of digital-signal symbolshaving prescribed ⅔ trellis coding, three-bit symbols of said ⅔ trelliscoding being mapped to said eight-level symbol alphabet in such manneras to generate binary-coded modulation superposed on said pedestal, atleast some said respective 312 further segments of said fields ofdigital-signal symbols including within selected portions thereofdigital-signal symbols generated by said prescribed ⅔ trellis codingresponding to M/H service data that has been randomized and encoded withan outer coding, two-bit symbols of which outer coding are subjected tosymbol interleaving and anti-Gray-coding before being ⅔ trellis coded,said receiver comprising: apparatus for receiving a selectedvestigial-sideband amplitude-modulation signal and converting it to abaseband digital signal including successive reproduced eight-levelsymbols of 12-phase ⅔ trellis-coded baseband digital signal; an innersoft-input/soft-output (SISO) decoder connected for trellis decodingsaid successive reproduced eight-level symbols of 12-phase ⅔trellis-coded baseband digital signal to generate an inner decoderresponse composed of soft decisions concerning two-bit symbolspreviously encoded within said eight-level symbols, each soft decisioncomposed of a-respective hard decision as to the value of each of saidtwo-bit symbols and an accompanying indication of the probability ofthat said respective two-bit symbol being correct; a first soft-decisionrecoder of the kind set forth in claim 37, connected for recoding onesof said soft decisions generated by said inner SISO decoder that concernanti-Gray-coded two-bit symbols of symbol-interleaved M/H service dataencoded with said outer coding, thus to generate soft decisionsregarding two-bit symbols of symbol-interleaved M/H service data encodedwith said outer coding; and a symbol de-interleaver connected forreceiving said soft decisions regarding two-bit symbols ofsymbol-interleaved M/H service data encoded with said outer coding andcomplementing said symbol interleaving to generate de-interleaved M/Hservice data encoded with said outer coding; and an outersoft-input/soft-output (SISO) decoder for said M/H service data encodedwith an outer coding connected for receiving said de-interleaved M/Hservice data encoded with said outer coding from said symbolde-interleaver and further decoding said de-interleaved M/H service datato generate soft decisions concerning bits of said M/H service data andaccompanying bits from said outer coding.
 3. The claim 2 receiver,further comprising: a symbol interleaver connected for receiving saidsoft decisions concerning bits of said M/H service data and accompanyingbits from said outer coding from said outer SISO decoder andsymbol-interleaving successive ones of them to generatesymbol-interleaved soft decisions of a symbol-interleaved turbo feedbacksignal; a second soft-decision recoder of the kind set forth in claim37, connected for recoding said symbol-interleaved soft decisions insaid symbol-interleaved turbo feedback signal to generatesymbol-interleaved soft decisions of an anti-Gray-codedsymbol-interleaved turbo feedback signal; and a comparator fordetermining anti-Gray-coded extrinsic information to modify operation ofsaid inner soft-input/soft-output decoder, said comparator beingconnected to determine said anti-Gray-coded extrinsic information bycomparing said anti-Gray-coded symbol-interleaved turbo feedback signalwith said inner SISO decoder response.
 4. The claim 3 receiver, furthercomprising: a hard-decision unit connected for generating successivehard decisions as to bits of said M/H service data responsive toportions of said soft decisions concerning bits of said M/H servicedata, which said soft decisions are generated by said outer SISOdecoder; an M/H Frame decoder connected for receiving as an input signalthereto said successive hard decisions as to bits of said M/H servicedata and for responding to supply data-randomized transport streampackets; and a data de-randomizer connected for receivingdata-randomized transport stream packets supplied from said M/H Framedecoder and de-randomizing them to supply restored transport streampackets.
 5. The claim 3 receiver as adapted for receiving M/H servicedata that has been bit de-interleaved in accordance with a prescribedbit de-interleaving pattern after having been randomized but beforehaving been encoded with said outer coding and subjected to symbolinterleaving, said receiver further comprising: a hard-decision unitconnected for generating successive hard decisions as to bits of saidM/H service data responsive to portions of said soft decisionsconcerning bits of said M/H service data, which said soft decisions aregenerated by said outer SISO decoder; a bit interleaver for interleavingsaid successive hard decisions in accordance with a bit-interleavingpattern complementary to said bit de-interleaving pattern, therebygenerating successive bit-interleaved hard decisions; an M/H Framedecoder connected for receiving as an input signal thereto saidsuccessive bit-interleaved hard decisions and for responding to supplydata-randomized transport stream packets; and a data de-randomizerconnected for receiving data-randomized transport stream packetssupplied from said M/H Frame decoder and de-randomizing them to supplyrestored transport stream packets.
 6. The claim 3 receiver as adaptedfor receiving M/H service data that has been bit de-interleaved inaccordance with a prescribed bit de-interleaving pattern after havingbeen randomized but before having been encoded with said outer codingand subjected to symbol interleaving, said receiver further comprising:a hard-decision unit connected for generating successive hard decisionsas to bits of said M/H service data responsive to portions of saidsymbol-interleaved soft decisions generated by said symbol interleaver;an M/H Frame decoder connected for receiving as an input signal theretosaid successive hard decisions as to bits of said M/H service data andfor responding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 7. The claim 2receiver, further comprising: a second soft-decision recoder of the kindset forth in claim 37, connected for generating soft decisionsconcerning an anti-Gray-coded turbo feedback signal by recoding saidsoft decisions generated by said outer SISO decoder; a symbolinterleaver connected for receiving said soft decisions concerning saidanti-Gray-coded turbo feedback signal and symbol-interleaving successiveones of them to generate symbol-interleaved soft decisions in asymbol-interleaved anti-Gray-coded turbo feedback signal; and acomparator for determining anti-Gray-coded extrinsic information tomodify operation of said inner SISO decoder, said comparator beingconnected to determine said anti-Gray-coded extrinsic information bycomparing said symbol-interleaved anti-Gray-coded turbo feedback signalwith said inner decoder response.
 8. The claim 7 receiver, furthercomprising: a hard-decision unit connected for generating successivehard decisions as to bits of said M/H service data responsive toportions of said soft decisions generated by said outer SISO decoder; anM/H Frame decoder connected for receiving as an input signal theretosaid successive hard decisions as to bits of said M/H service data andfor responding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 9. The claim 7receiver as adapted for receiving M/H service data that has been bitde-interleaved in accordance with a prescribed bit de-interleavingpattern after having been randomized but before having been encoded withsaid outer coding and subjected to symbol interleaving, said receiverfurther comprising: a hard-decision unit connected for generatingsuccessive hard decisions as to bits of said M/H service data responsiveto portions of said soft decisions generated by said outer SISO decoder;a bit interleaver for interleaving said successive hard decisions inaccordance with a bit-interleaving pattern complementary to said bitde-interleaving pattern, thereby generating successive bit-interleavedhard decisions; an M/H Frame decoder connected for receiving as an inputsignal thereto said successive bit-interleaved hard decisions and forresponding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 10. The claim 2receiver, further comprising: a symbol interleaver connected forreceiving said soft decisions generated by said outer SISO decoder andsymbol-interleaving successive ones of them to generate successivesymbol-interleaved soft decisions within a symbol-interleaved turbofeedback signal; a comparator for determining extrinsic information bycomparing soft decisions in said symbol-interleaved turbo feedbacksignal with said soft decisions regarding two-bit symbols ofsymbol-interleaved M/H service data encoded with said outer coding assupplied to said symbol de-interleaver; and a second soft-decisionrecoder of the kind set forth in claim 37, connected for recodingtwo-bit symbols of said extrinsic information to generateanti-Gray-coded extrinsic information supplied to said inner SISOdecoder to modify its operation.
 11. The claim 10 receiver, furthercomprising: a hard-decision unit connected for generating successivehard decisions as to bits of said M/H service data responsive toportions of said soft decisions generated by said outer SISO decoder; anM/H Frame decoder connected for receiving as an input signal theretosaid successive hard decisions as to bits of said M/H service data andfor responding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 12. The claim 10receiver as adapted for receiving M/H service data that has been bitde-interleaved in accordance with a prescribed bit de-interleavingpattern after having been randomized but before having been encoded withsaid outer coding and subjected to symbol interleaving, said receiverfurther comprising: a hard-decision unit connected for generatingsuccessive hard decisions as to bits of said M/H service data responsiveto portions of said soft decisions generated by said outer SISO decoder;a bit interleaver for interleaving said successive hard decisions inaccordance with a bit-interleaving pattern complementary to said bitde-interleaving pattern, thereby generating successive bit-interleavedhard decisions; an M/H Frame decoder connected for receiving as an inputsignal thereto said successive bit-interleaved hard decisions and forresponding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 13. The claim 10receiver as adapted for receiving M/H service data that has been bitde-interleaved in accordance with a prescribed bit de-interleavingpattern after having been randomized but before having been encoded withsaid outer coding and subjected to symbol interleaving, said receiverfurther comprising: a hard-decision unit connected for generatingsuccessive hard decisions as to bits of said M/H service data responsiveto portions of said symbol-interleaved soft decisions generated by saidsymbol interleaver; an M/H Frame decoder connected for receiving as aninput signal thereto said successive hard decisions and for respondingto supply data-randomized transport stream packets; and a datade-randomizer connected for receiving data-randomized transport streampackets supplied from said M/H Frame decoder and de-randomizing them tosupply restored transport stream packets.
 14. The claim 2 receiver,further comprising: a comparator for determining de-interleavedextrinsic information, said comparator being connected to determine saidde-interleaved extrinsic information by comparing soft decisionsregarding M/H service data encoded with said outer coding as suppliedfrom said symbol de-interleaver with said soft decisions generated bysaid outer SISO decoder; a symbol interleaver connected for receivingsaid de-interleaved extrinsic information as determined by saidcomparator and symbol-interleaving successive two-soft-bit symbols ofsaid de-interleaved extrinsic information to generate successivetwo-soft-bit symbols of symbol-interleaved extrinsic information; and asecond soft-decision recoder of the kind set forth in claim 37,connected for being addressed by at least successive two-soft-bit datasymbol portions of said symbol-interleaved extrinsic information, saidsecond soft-decision recoder anti-Gray coding said successivetwo-soft-bit symbols of said symbol-interleaved extrinsic information togenerate successive two-soft-bit symbols of anti-Gray-coded extrinsicinformation supplied to said inner SISO decoder to modify its operation.15. The claim 14 receiver, further comprising: a hard-decision unitconnected for generating successive hard decisions as to bits of saidM/H service data responsive to portions of said soft decisions generatedby said outer SISO decoder; an M/H Frame decoder connected for receivingas an input signal thereto said successive hard decisions as to bits ofsaid M/H service data and for responding to supply data-randomizedtransport stream packets; and a data de-randomizer connected forreceiving data-randomized transport stream packets supplied from saidM/H Frame decoder and de-randomizing them to supply restored transportstream packets.
 16. The claim 14 receiver as adapted for receiving M/Hservice data that has been bit de-interleaved in accordance with aprescribed bit de-interleaving pattern after having been randomized butbefore having been encoded with said outer coding and subjected tosymbol interleaving, said receiver further comprising: a hard-decisionunit connected for generating successive hard decisions as to bits ofsaid MI/H service data responsive to portions of said soft decisionsgenerated by said outer SISO decoder; a bit interleaver for interleavingsaid successive hard decisions in accordance with a bit-interleavingpattern complementary to said bit de-interleaving pattern, therebygenerating successive bit-interleaved hard decisions; an M/H Framedecoder connected for receiving as an input signal thereto saidsuccessive bit-interleaved hard decisions and for responding to supplydata-randomized transport stream packets; and a data de-randomizerconnected for receiving data-randomized transport stream packetssupplied from said M/H Frame decoder and de-randomizing them to supplyrestored transport stream packets.
 17. The claim 2 receiver, furthercomprising: a comparator for determining de-interleaved extrinsicinformation, said comparator being connected to determine two-soft-bitsymbols of said de-interleaved extrinsic information by comparing softdecisions regarding two-bit symbols of M/H service data encoded withsaid outer coding as supplied from said symbol de-interleaver with saidsoft decisions regarding two-bit symbols of M/H service data encodedwith said outer coding as supplied from said outer SISO decoder; asecond soft-decision recoder of the kind set forth in claim 37,connected for being addressed by two-soft-bit symbols of saidde-interleaved extrinsic information, said second read-only memoryanti-Gray coding each respective two-soft-bit symbol of saidde-interleaved extrinsic information to generate a respectivetwo-soft-bit symbol of anti-Gray-coded de-interleaved extrinsicinformation; and a symbol interleaver connected for receiving successivesaid two-soft-bit symbols of anti-Gray-coded de-interleaved extrinsicinformation and symbol-interleaving successive ones of them to generatetwo-soft-bit symbols of symbol-interleaved anti-Gray-coded extrinsicinformation supplied to said inner SISO decoder to modify its operation.18. The claim 17 receiver, further comprising: a hard-decision unitconnected for generating successive hard decisions as to bits of saidM/H service data responsive to portions of said soft decisions generatedby said outer SISO decoder; an M/H Frame decoder connected for receivingas an input signal thereto said successive hard decisions as to bits ofsaid M/H service data and for responding to supply data-randomizedtransport stream packets; and a data de-randomizer connected forreceiving data-randomized transport stream packets supplied from saidM/H Frame decoder and de-randomizing them to supply restored transportstream packets.
 19. The claim 17 receiver as adapted for receiving M/Hservice data that has been bit de-interleaved in accordance with aprescribed bit de-interleaving pattern after having been randomized butbefore having been encoded with said outer coding and subjected tosymbol interleaving, said receiver further comprising: a hard-decisionunit connected for generating successive hard decisions as to bits ofsaid M/H service data responsive to portions of said soft decisionsgenerated by said outer SISO decoder; a bit interleaver for interleavingsaid successive hard decisions in accordance with a bit-interleavingpattern complementary to said bit de-interleaving pattern, therebygenerating successive bit-interleaved hard decisions; an M/H Framedecoder connected for receiving as an input signal thereto saidsuccessive bit-interleaved hard decisions and for responding to supplydata-randomized transport stream packets; and a data de-randomizerconnected for receiving data-randomized transport stream packetssupplied from said M/H Frame decoder and de-randomizing them to supplyrestored transport stream packets.
 20. A receiver for vestigial-sidebandamplitude-modulation (VSB AM) signal, successive symbols of themodulating signal for said VSB AM signal defining a digital signal inaccordance with an eight-level symbol alphabet superposed on a pedestal,said digital signal composed of successive frames each composed of tworespective fields of digital-signal symbols, each said field composed ofa respective initial segment of 832 digital-signal symbols succeeded byrespective 312 consecutive further segments of 832 digital-signalsymbols apiece, the four initial digital-signal symbols of each of saidsegments of 832 digital-signal symbols being a prescribed data segmentsynchronizing signal sequence, the final 828 digital-signal symbols ofsaid 312 further segments of each said field of digital-signal symbolshaving prescribed ⅔ trellis coding, three-bit symbols of said ⅔ trelliscoding being mapped to said eight-level symbol alphabet in such manneras to generate binary-coded modulation superposed on said pedestal, atleast some said respective 312 further segments of said fields ofdigital-signal symbols including within selected portions thereofdigital-signal symbols generated by said prescribed ⅔ trellis codingresponding to M/H service data that has been randomized and encoded withan outer coding, two-bit symbols of which outer coding are subjected tosymbol interleaving and anti-Gray-coding before being ⅔ trellis coded,said receiver comprising: apparatus for receiving a selectedvestigial-sideband amplitude-modulation signal and converting it to abaseband digital signal including successive reproduced eight-levelsymbols of 12-phase ⅔ trellis-coded baseband digital signal, an innersoft-input/soft-output (SISO) decoder connected for trellis decodingsaid successive reproduced eight-level symbols of 12-phase ⅔trellis-coded baseband digital signal to generate an inner decoderresponse composed of soft decisions concerning two-bit symbolspreviously encoded within said eight-level symbols, each soft decisioncomposed of a respective hard decision as to the value of each of saidtwo-bit symbols and an accompanying indication of the probability ofthat said respective two-bit symbol being correct; a symbolde-interleaver connected for receiving said soft decisions generated bysaid inner SISO decoder and complementing said symbol interleaving tosupply de-interleaved soft decisions; a first soft-decision recoder ofthe kind set forth in claim 37, connected for recoding saidde-interleaved soft decisions supplied from said symbol de-interleaverto generate recoded de-interleaved soft decisions; and an outersoft-input/soft-output (SISO) decoder for said M/H service data encodedwith an outer coding connected for receiving said recoded de-interleavedsoft decisions and further decoding said recoded de-interleaved softdecisions as so received to generate soft decisions concerning said bitsof said M/H service data and accompanying bits from said outer coding.21. The claim 20 receiver, further comprising: a symbol interleaverconnected for receiving said soft decisions concerning two-bit symbolsof said M/H service data from said outer SISO decoder andsymbol-interleaving successive ones of them to generatesymbol-interleaved soft decisions of a symbol-interleaved turbo feedbacksignal; a second soft-decision recoder of the kind set forth in claim37, connected for recoding said symbol-interleaved soft decisions insaid symbol-interleaved turbo feedback signal to generatesymbol-interleaved soft decisions of an anti-Gray-codedsymbol-interleaved turbo feedback signal; and a comparator fordetermining anti-Gray-coded extrinsic information to modify operation ofsaid inner soft-input/soft-output decoder, said comparator beingconnected to determine said anti-Gray-coded extrinsic information bycomparing said anti-Gray-coded symbol-interleaved turbo feedback signalwith said inner SISO decoder response.
 22. The claim 21 receiver,further comprising: a hard-decision unit connected for generatingsuccessive hard decisions as to bits of said M/H service data responsiveto portions of said soft decisions generated by said outer SISO decoder;an M/H Frame decoder connected for receiving as an input signal theretosaid successive hard decisions as to bits of said M/H service data andfor responding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 23. The claim 21receiver as adapted for receiving M/H service data that has been bitde-interleaved in accordance with a prescribed bit de-interleavingpattern after having been randomized but before having been encoded withsaid outer coding and subjected to symbol interleaving, said receiverfurther comprising: a hard-decision unit connected for generatingsuccessive hard decisions as to bits of said M/H service data responsiveto portions of said soft decisions generated by said outer SISO decoder;a bit interleaver for interleaving said successive hard decisions inaccordance with a bit-interleaving pattern complementary to said bitde-interleaving pattern, thereby generating successive bit-interleavedhard decisions; an M/H Frame decoder connected for receiving as an inputsignal thereto said successive bit-interleaved hard decisions and forresponding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 24. The claim 21receiver as adapted for receiving M/H service data that has been bitde-interleaved in accordance with a prescribed bit de-interleavingpattern after having been randomized but before having been encoded withsaid outer coding and subjected to symbol interleaving, said receiverfurther comprising: a hard-decision unit connected for generatingsuccessive hard decisions as to bits of said M/H service data responsiveto portions of said symbol-interleaved soft decisions generated by saidsymbol interleaver; an M/H Frame decoder connected for receiving as aninput signal thereto said successive hard decisions as to bits of saidM/H service data and for responding to supply data-randomized transportstream packets; and a data de-randomizer connected for receivingdata-randomized transport stream packets supplied from said M/H Framedecoder and de-randomizing them to supply restored transport streampackets.
 25. The claim 20 receiver, further comprising: a secondsoft-decision recoder of the kind set forth in claim 37, connected forgenerating soft decisions concerning two-bit symbols of ananti-Gray-coded turbo feedback signal by recoding said soft decisionsgenerated by said outer SISO decoder; a symbol interleaver connected forreceiving said soft decisions concerning two-bit symbols of saidanti-Gray-coded turbo feedback signal and symbol-interleaving successiveones of them to generate symbol-interleaved soft decisions in asymbol-interleaved anti-Gray-coded turbo feedback signal; and acomparator for determining anti-Gray-coded extrinsic information tomodify operation of said inner SISO decoder, said comparator beingconnected to determine said anti-Gray-coded extrinsic information bycomparing said symbol-interleaved anti-Gray-coded turbo feedback signalwith said inner decoder response.
 26. The claim 25 receiver, furthercomprising: a hard-decision unit connected for generating successivehard decisions as to bits of said M/H service data responsive toportions of said soft decisions generated by said outer SISO decoder; anM/H Frame decoder connected for receiving as an input signal theretosaid successive hard decisions as to bits of said M/H service data andfor responding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 27. The claim 25receiver as adapted for receiving MI/H service data that has been bitde-interleaved in accordance with a prescribed bit de-interleavingpattern after having been randomized but before having been encoded withsaid outer coding and subjected to symbol interleaving, said receiverfurther comprising: a hard-decision unit connected for generatingsuccessive hard decisions as to bits of said M/H service data responsiveto portions of said soft decisions generated by said outer SISO decoder;a bit interleaver for interleaving said successive hard decisions inaccordance with a bit-interleaving pattern complementary to said bitde-interleaving pattern, thereby generating successive bit-interleavedhard decisions; an M/H Frame decoder connected for receiving as an inputsignal thereto said successive bit-interleaved hard decisions and forresponding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 28. The claim 20receiver, further comprising: a second soft-decision recoder of the kindset forth in claim 37, connected for generating soft decisionsconcerning an anti-Gray-coded turbo feedback signal by recoding saidsoft decisions generated by said outer SISO decoder; a comparator fordetermining de-interleaved anti-Gray-coded extrinsic information, saidcomparator being connected to determine successive two-soft-bit symbolsof said de-interleaved anti-Gray-coded extrinsic information bycomparing successive two-soft-bit symbols of said anti-Gray-coded turbofeedback signal with two-soft-bit symbols of M/H service data encodedwith said outer coding as supplied from said symbol de-interleaver; anda symbol interleaver connected for receiving successive said successivetwo-soft-bit symbols of said de-interleaved anti-Gray-coded extrinsicinformation from said comparator and symbol-interleaving them togenerate successive two-soft-bit symbols of symbol-interleavedanti-Gray-coded extrinsic information supplied to said inner SISOdecoder to modify its operation.
 29. The claim 28 receiver, furthercomprising: a hard-decision unit connected for generating successivehard decisions as to bits of said M/H service data responsive toportions of said soft decisions generated by said outer SISO decoder; anM/H Frame decoder connected for receiving as an input signal theretosaid successive hard decisions as to bits of said M/H service data andfor responding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 30. The claim 28receiver as adapted for receiving M/H service data that has been bitde-interleaved in accordance with a prescribed bit de-interleavingpattern after having been randomized but before having been encoded withsaid outer coding and subjected to symbol interleaving, said receiverfurther comprising: a hard-decision unit connected for generatingsuccessive hard decisions as to bits of said M/H service data responsiveto portions of said soft decisions generated by said outer SISO decoder;a bit interleaver for interleaving said successive hard decisions inaccordance with a bit-interleaving pattern complementary to said bitde-interleaving pattern, thereby generating successive bit-interleavedhard decisions; an M/H Frame decoder connected for receiving as an inputsignal thereto said successive bit-interleaved hard decisions and forresponding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 31. The claim 20receiver, further comprising: a comparator for determiningde-interleaved extrinsic information, said comparator being connected todetermine said de-interleaved extrinsic information by comparing softdecisions supplied from said symbol de-interleaver with said softdecisions generated by said outer SISO decoder; a symbol interleaverconnected for receiving said de-interleaved extrinsic information asdetermined by said comparator and symbol-interleaving successivetwo-soft-bit symbols of said de-interleaved extrinsic information togenerate successive two-soft-bit symbols of symbol-interleaved extrinsicinformation; and a second soft-decision recoder of the kind set forth inclaim 37, connected for being addressed by at least successivetwo-soft-bit data symbol portions of said symbol-interleaved extrinsicinformation, said second soft-decision recoder anti-Gray coding saidsuccessive two-soft-bit symbols of said symbol-interleaved extrinsicinformation to generate successive two-soft-bit symbols ofanti-Gray-coded extrinsic information supplied to said inner SISOdecoder to modify its operation.
 32. The claim 31 receiver, furthercomprising: a hard-decision unit connected for generating successivehard decisions as to bits of said M/H service data responsive toportions of said soft decisions generated by said outer SISO decoder; anM/H Frame decoder connected for receiving as an input signal theretosaid successive hard decisions as to bits of said M/H service data andfor responding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 33. The claim 31receiver as adapted for receiving M/H service data that has been bitde-interleaved in accordance with a prescribed bit de-interleavingpattern after having been randomized but before having been encoded withsaid outer coding and subjected to symbol interleaving, said receiverfurther comprising: a hard-decision unit connected for generatingsuccessive hard decisions as to bits of said M/H service data responsiveto portions of said soft decisions generated by said outer SISO decoder;a bit interleaver for interleaving said successive hard decisions inaccordance with a bit-interleaving pattern complementary to said bitde-interleaving pattern, thereby generating successive bit-interleavedhard decisions; an M/H Frame decoder connected for receiving as an inputsignal thereto said successive bit-interleaved hard decisions and forresponding to supply data-randomized transport stream packets; and adata de-randomizer connected for receiving data-randomized transportstream packets supplied from said M/H Frame decoder and de-randomizingthem to supply restored transport stream packets.
 34. The claim 20receiver, further comprising: a comparator for determiningde-interleaved extrinsic information, said comparator being connected todetermine two-soft-bit symbols of said de-interleaved extrinsicinformation by comparing soft decisions regarding two-bit symbols of M/Hservice data encoded with said outer coding as supplied from said symbolde-interleaver with said soft decisions regarding two-bit symbols of M/Hservice data encoded with said outer coding as supplied from said outerSISO decoder; a second soft-decision recoder of the kind set forth inclaim 37, connected for being addressed by two-soft-bit symbols of saidde-interleaved extrinsic information, said second read-only memoryanti-Gray coding each respective two-soft-bit symbol of saidde-interleaved extrinsic information to generate a respectivetwo-soft-bit symbol of anti-Gray-coded de-interleaved extrinsicinformation; and a symbol interleaver connected for receiving successivesaid two-bit symbols of anti-Gray-coded de-interleaved extrinsicinformation and symbol-interleaving successive ones of them to generatesymbol-interleaved anti-Gray-coded extrinsic information supplied tosaid inner SISO decoder to modify its operation.
 35. The claim 34receiver, further comprising: a hard-decision unit connected forgenerating successive hard decisions as to bits of said M/H service dataresponsive to portions of said soft decisions generated by said outerSISO decoder; an M/H Frame decoder connected for receiving as an inputsignal thereto said successive hard decisions as to bits of said M/Hservice data and for responding to supply data-randomized transportstream packets; and a data de-randomizer connected for receivingdata-randomized transport stream packets supplied from said M/H Framedecoder and de-randomizing them to supply restored transport streampackets.
 36. The claim 34 receiver as adapted for receiving M/H servicedata that has been bit de-interleaved in accordance with a prescribedbit de-interleaving pattern after having been randomized but beforehaving been encoded with said outer coding and subjected to symbolinterleaving, said receiver further comprising: a hard-decision unitconnected for generating successive hard decisions as to bits of saidM/H service data responsive to portions of said soft decisions generatedby said outer SISO decoder; a bit interleaver for interleaving saidsuccessive hard decisions in accordance with a bit-interleaving patterncomplementary to said bit de-interleaving pattern, thereby generatingsuccessive bit-interleaved hard decisions; an M/H Frame decoderconnected for receiving as an input signal thereto said successivebit-interleaved hard decisions and for responding to supplydata-randomized transport stream packets; and a data de-randomizerconnected for receiving data-randomized transport stream packetssupplied from said Mi/H Frame decoder and de-randomizing them to supplyrestored transport stream packets.
 37. A soft-decision recoder forrecoding a first succession of soft decisions each composed of arespective pair of soft bits to generate a second succession of softdecisions each composed of a respective pair of soft bits, each of saidsoft bits consisting of first through nth bits, the first of each ofsaid soft bits consisting of a respective hard bit and the secondthrough nth of each of said soft bits indicative of the likelihood ofits said respective hard bit being correct, said soft-decision recodercomprising: a plurality n in number of logic gates, each of said logicgates connected to receive as a respective first input signal theretosaid respective hard bits of first ones of each of said pairs of softbits in said first succession of soft decisions, the first through nthones of said logic gates connected to receive as respective inputsignals thereto respective ones of the first through nth bits of secondones of each of said pairs of soft bits in said first succession of softdecisions; wherein the first through nth bits of first ones of each ofsaid pairs of soft bits in said second succession of soft decisions arederived from the first through nth bits of first ones of each of saidpairs of soft bits in said first succession of soft decisions; andwherein the first through nth bits of second ones of each of said pairsof soft bits in said second succession of soft decisions are derivedfrom the responses of the first through nth ones of said logic gatesrespectively.
 38. The claim 37 soft-decision recoder, wherein each ofsaid logic gates n in number is a respective exclusive-OR gate, whereinthe first through nth bits of first ones of each of said pairs of softbits in said second succession of soft decisions correspond to the firstthrough nth bits of first ones of each of said pairs of soft bits insaid first succession of soft decisions, and wherein the first throughnth bits of second ones of each of said pairs of soft bits in saidsecond succession of soft decisions correspond to the responses of thefirst through nth ones of said logic gates respectively.
 39. The claim37 soft-decision recoder, wherein each of said logic gates n in numberis a respective exclusive-NOR gate, wherein the first through nth bitsof first ones of each of said pairs of soft bits in said secondsuccession of soft decisions correspond to the first through nth bits offirst ones of each of said pairs of soft bits in said first successionof soft decisions, and wherein the first through nth bits of second onesof each of said pairs of soft bits in said second succession of softdecisions correspond to the responses of the first through nth ones ofsaid logic gates respectively.